Present day computer networks today involve the interconnection of many types of digital modules which are required to communicate with each other both as a sender and a receiver.
A typical example of a complex network is shown in FIG. 2 where a system bus 10 connects a series of digital modules such as an A Series Central Processor (Unisys) Module 12, a Main Memory 14, a Processor Unit 18 10 such as an Intel (P6) Pentium or Pentium Pro. The system bus 10 is connected to system bus bridge units 22 and 24 which connect to other networks. Thus, bus 10b connects the system bus 10 to the I/O bus 20. The I/O bus 20 is here called a PCI bus. The PCI bus 20 connects another series of digital modules shown as an Input/Output Module 28, (IOM 2), an Auxiliary Message Arbitration Unit AMA 30, and another bridge unit 32 designated as PCI-EISA Bridge. The bridge unit 32 connects to a standard EISA bus 32e which connects to other EISA peripheral units designated 36.
In FIG. 2, the Input/Output Module, IOM 28, includes a group of digital modules designated as the Task Control Unit, TCU 42, Input/Output Unit IOU, 44, and Channel Manager Unit, CMU 46.
In the digital network shown in FIG. 2, it is necessary that a suitable protocol and proper control of message transfers be arranged for optimum operation of the system.
Present technology has made it possible to interconnect many digital modules such as processors, memories and Input/Output units in order to build powerful and effective computer systems. The performance of such multi-digital network systems depends on many factors such as the control of message flow, the scheduling and the interconnection methods used between the various digital modules, and also the implementation of fault free communication between modules.
One of the significant problems in message passing is the orderly and efficient transfer of messages from one digital module to another, and also the feature of message preservation when delivery of a message is not possible. Certain problematic conditions occur in networks which utilize both hardware modules and software modules. Basically, hardware modules when running uninterrupted work fast in handling and processing the data that is passed through them. On the other hand, software modules operating on a time-shared operating system are not completely dedicated to one type of operation, but are involved with task switching into different programs from time to time and thus, one earlier program may be delayed because the software is running on a second program and has not yet returned to the first program.
Thus, systems which used software solutions to try to handle the orderly transmission of messages ran into considerable difficulties. Some of these software solutions involved link lists in memory and assigned a number in memory to each message so that the messages would be accessed sequentially according to the number of the message. Then when that numbered message was used, the number was incremented and placed back in memory.
On these types of solutions using software, the queuing solution and the incrementing number solution leads to difficulties when you have multiple senders. Then it is necessary to make arrangements to see that the various sending modules are coordinated and not in conflict with each other. If a link list is built, it is not possible then to have two senders putting something into the list at the same time where they could interfere with each other.
Likewise, if there were two senders looking at a particular message number, the system would have to do something to prevent the senders from getting the same value of the number for their messages. Since there is a finite time from when the first sender gets the number, until he increments it and stores it back, then if the second sender asks for a number during that interval, the second sender is going to get the same number as the first sender and they both will put their messages in the same slot number. Thus, one sender will wipe out the message of the other sender.
It would be possible to prevent some of the software problems by having locking operations in memory, but again the problem with locking operations occurs when one software module obtains the lock which prevents other modules from doing anything until that module uses the lock, then the platform operating system takes the processor for some period of time causing every other sender to wait until a sender gets the processor back in order to do what is necessary to release the lock.
The present system provides a module which operates in a dedicated fashion as hardware to handle the message transmission control operations and the hardware responds rapidly and quickly since it does not have any need for a locking operation, because it is atomic, and because it guarantees that the two senders will not get the same number value. Thus, there is a fast certain and definite chronological system for message transfers that is done rapidly through hardware control modules, while at the same time it still can handle and be responsive to software modules operating in the system, thus allowing a mixture of hardware and software modules without the software modules slowing down the system.